Refine your search
Collections
Co-Authors
Journals
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Il, Han
- An Implementation of Multi-DSP System Architecture for Processing Variant Length Frame for Weather Radar
Abstract Views :263 |
PDF Views:0
Authors
Affiliations
1 Institute of Information Science, Kim Il Sung University, D.P.R. of Korea, KP
1 Institute of Information Science, Kim Il Sung University, D.P.R. of Korea, KP
Source
ICTACT Journal on Microelectronics, Vol 4, No 1 (2018), Pagination: 547-551Abstract
In this paper we propose a method for implementation of multi-DSP system which four DSPs are coupled by FPGA for processing variant length frame and noise and showed experimental results. This system receives variant length frame from EDMA and McBSP and increases parallel processing speed. This device has wide prospect in signal processing system, sonar, real-time image processing system.Keywords
DSP, FPGA, Digital Signal Processing System, Variant Length Frame, PD Radar.
References
- TMS320C6000 User’s Guide, Available at: http://www.ti.com/lit/ug/spru303b/spru303b.pdf.
- C. Victor and Chen Hao Ling, “Time-Frequency Transforms for Radar Imaging and Signal Analysis”, Artech House, 2002.
- Wei Wu et al., “Design methods of Multi-DSP Parallel Processing System”, Proceedings of World Congress on Computer Science and Information Engineering, Vol. 3, pp. 458-464, 2009.
- Fan Xikun et al., “Real-Time Implementation of Airborne Radar Space-Time Adaptive Processing on Multi-DSP System”, Proceedings of IEEE Conference on Radar, pp. 481-486, 2006.
- Mukul Khandelia et al., “Contention-Conscious Transaction Ordering in Multiprocessor DSP Systems”, IEEE Transactions on Signal Processing, Vol. 54, No. 2, 2006.
- Yi-Hsuan Lee et al., “A Two-Level Scheduling Method: An Effective Parallelizing Technique for Uniform Nested Loops on a DSP Multiprocessor”, Journal of Systems and Software, Vol. 75, No. 1, pp. 155-170, 2005.
- T. Lothar et al., “Performance Analysis of Multiprocessor DSPs: A Stream-Oriented Component Model”, IEEE Signal Processing Magazine, Vol. 22, No. 3, pp. 38-46, 2005.
- Mao Hai-Cen, et al., “A Flexible DSP-Based Network for Real-Time Image-Processing”, Wuhan University Journal of Natural Sciences, Vol. 9, No. 6, pp. 921-926, 2004.
- Xiang Hong, “Parallel Implementation of High Resolution Radar Signal Processing System Based On Multi-IC Architecture”, Proceedings of IEEE Conference on Radar, pp. 812-815, 2013.
- Zhang Huixin, He Qi Liusuhua and Yang Haiguang, “The Design for LVDS High speed Data Acquisition and Transmission System based on FPGA”, Proceedings of IEEE Conference on Radar, pp. 383-386, 2011.
- Yuan Changshun et al., “A Novel Design of Parallel and High-Speed Signal Processor Architecture for PD Radar”, Proceedings of IEEE Conference on Radar, pp. 551-556, 2013.
- Man Li, et al., “Research on Parallel Debugger in Bus-Based Multi-DSP System in Radar Data Processing”, Proceedings of IEEE Conference on Radar, pp. 236-241, 2013.